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XTS-AES Core - Encryption of Stored Data
This highly configurable implementation of the XTS-AES algorithm for storage encryption implements the full NIST SP800-38E specification used in IEEE standard 1619-2007. AES XTS is based on a pipelined implementation of AES to provide throughput to match multi-gigabit storage connection schemes such as USB 3.0 and SATA 3.0.
The AES-XTS core is based on our NIST validated AES-G3 implementation and is supplied as a complete package of VHDL or Verilog source code. The number of pipelined AES encryptors is configurable allowing a flexible tradeoff of area against performance.
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AES XTS Core |
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Internal and External Data Path Width |
128 bits |
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Cipher Modes |
XTS, (if required ECB, CBC, CFB, OFB, CTR can be added) |
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Functions |
Encrypt, Decrypt, Encrypt/Decrypt |
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Key Lengths |
128, 256 bit AES Keys (256, 512 bit XTS-AES keys) |
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Keyschedule Calculation |
Hardware keyschedule calculation. |
Datasheets:
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