G3 AES Core - AES Encryption IP Core for FPGAs - Reference Design for Altera NIOS Processor

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New AES IP core implements the XTS-AES algorithm used in the IEEE 1619-2007 and NIST SP800-38E standards for encrypted data storage. .

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AES G3 Reference Design for Altera NIOS Processor

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Product Code: AES-ALTERA-REF

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Altera(Members Only)]

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AES G3 Reference Design for Altera NIOS Processor

This reference design runs on Altera's DE2 Evaluation board and interfaces to a PC over USB. It demonstrates the AES-G3 core interfaced to a NIOS processor to accelerate AES encryption.

Datasheets:

AES G3 and Altera NIOS Processor Reference Design

Features

Complete reference design for Altera DE2 Evaluation Board
DE2 board implements an embedded encryption system interfaced to a PC via USB
PC software allows files to be sent to the DE2 board to be encrypted using the AES-G3 core