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AES G3 Reference Design for Xilinx Processors

• A hardware interface using Xilinx's CoreConnect bus standard which ‘wraps’ the AES-G3 core and allows it to be integrated into larger systems using Xilinx’s XPS software. The main function of this hardware is to provide flow control, starting and stopping the very fast hardware AES Encryptor as data becomes available from the much slower embedded software running on the MicroBlaze (or PowerPC) processor.
• Embedded software running on the MicroBlaze processor which provides a connection to a PC via an ethernet network and transfers data to and from the AES-G3 encryptor. The MicroBlaze board obtains an IP address from the network via DHCP and can therefore communicate with any PC on the network. This software was created by modifying and adding capabilities to an ethernet reference design supplied by Xilinx.
• An application running on the PC which allows the user to select files and transfer them to the Spartan 3A board for encryption. The application also provides a GUI for specifying the encryption key and Initial Value (IV) and includes a software implementation of AES so that results from the Spartan 3A board can be verified.

This product does not include the Xilinx Spartan 3A board which is required to run the design: this board is relatively inexpensive and can be purchased from Xilinx.

This product does not include a license for 'production' use of the AES-G3 core which must be purchased separately.

Free evaluation copies of AES-G3 and this product are available to qualified customers: use the discount code EVAL on the web order form or contact Algotronix by e-mail at sales@algotronix.com.