AES Keywrap Core - AES Encryption IP Core for FPGAs

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New AES-XTS IP Core

New AES IP core implements the XTS-AES algorithm used in the IEEE 1619-2007 and NIST SP800-38E standards for encrypted data storage. .

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AES Keywrap Core

Our Price: (Members Only)

Product Code: AES-CORE-KEYWRAP

Target Technology*:		Actel(Members Only)] Altera(Members Only)] Lattice(Members Only)] Platinum - All FPGA Vendors [Add (Members Only)] Xilinx(Members Only)]
Implementation Language*:		Both VHDL and Verilog (option available for multi-project licenses only) [Add (Members Only)] Verilog(Members Only)] VHDL(Members Only)]

Description

Ordering Information

This product includes the AES-G3 AES core. If you already have an AES-G3 license for your project then please contact us for reduced pricing on Keywrap.

For an unlimited use multi-project site license set order quantity to 2 and enter discount code SITE on the checkout page.

If you have previously purchased a project license for the core and wish to use it in another project enter discount code REUSE on the checkout page.

For further information, or to discuss your requirements, please contact us at sales@algotronix.com.