AES Core Demonstration Bitstream
This product is the compiled bitstream for the design in our Getting Started application note for the G2 and G3 AES cores. It demonstrates the G2 or G3 AES core on an FPGA manufacturer evaluation board calculating one of the standard AES test vectors from the FIPS 197 standard and displaying the result. Bitstreams are available off the shelf for Xilinx Spartan 3, Spartan 3A and Spartan 3E evaluation boards and for the Altera NIOS II evaluation board. This demonstration product is a fixed compiled bitstream which carries out one particular encryption where the key and plaintext are fixed and published in the FIPS 197 standard and displays the result. The product cannot be modified or incorporated in a larger design and it cannot be used to encrypt user specified data. As a generally available, fixed function, off the shelf product which does not allow user modification this product is not subject to the export licensing restrictions of the full-function AES core products and therefore may be useful to customers who wish to see a demonstration before applying for an export license for the full product. The product does not include the FPGA vendor evaluation board. Free evaluation copies of the product are available to qualified customers. |
