G3 AES Core - AES Encryption IP Core for FPGAs - Reference Design for Xilinx MicroBlaze Processor

New AES-XTS IP Core

New AES IP core implements the XTS-AES algorithm used in the IEEE 1619-2007 and NIST SP800-38E standards for encrypted data storage. .

AES G3 Reference Design for Xilinx Processors

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Product Code: AES-XILINX-REF

Technical Specs

Ordering Information

A hardware interface using Xilinx's CoreConnect bus standard which �wraps� the AES-G3 core and allows it to be integrated into larger systems using Xilinx�s XPS software. The main function of this hardware is to provide flow control, starting and stopping the very fast hardware AES Encryptor as data becomes available from the much slower embedded software running on the MicroBlaze (or PowerPC) processor.
Embedded software running on the MicroBlaze processor which provides a connection to a PC via an ethernet network and transfers data to and from the AES-G3 encryptor. The MicroBlaze board obtains an IP address from the network via DHCP and can therefore communicate with any PC on the network. This software was created by modifying and adding capabilities to an ethernet reference design supplied by Xilinx.
An application running on the PC which allows the user to select files and transfer them to the Spartan 3A board for encryption. The application also provides a GUI for specifying the encryption key and Initial Value (IV) and includes a software implementation of AES so that results from the Spartan 3A board can be verified.