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AES Core G3
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G3 Advanced Encryption Standard (AES) Core with parameterisable internal datapath width to allow a wide range of performance/area tradeoffs.
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AES Core G2
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G2 Advanced Encryption Standard (AES) Core with NIST validation certificate and 32 bit internal datapath width.
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AES Core Demonstration Bitstream
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This product is the compiled bitstream for the design in our Getting Started application note for the G2 and G3 AES cores. It demonstrates the G2 or G3 AES core on an FPGA manufacturer evaluation board calculating one of the standard AES test vectors from the FIPS 197 standard and displaying the result. Bitstreams are available off the shelf for Xilinx Spartan 3, Spartan 3A and Spartan 3E evaluation boards and for the Altera NIOS II evaluation board.
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AES Core GCM
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AES-GCM IP Core implementing full NIST Draft SP800-38D including 128, 192, 256 bit keys and variable length Initial Value (IV).
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AES Core GCM for IEEE 802.1 MACSEC at 10Gbit/sec
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Performance optimised AES-GCM core implementing AES-GCM as required by IEEE 802.1 MACSEC with fixed 128 bit key and 96 bit IV. Core achieves 10Gbit/sec performance under worst case traffic conditions on a Xilinx Virtex 5 FPGA.
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Extend Design-In Support for 12 months
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Algotronix' AES cores are provided with 1 year of product maintenance and design in support as standard. This product extends the support for an additional year.
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