AES Core XTS

AES Core XTS
Product Code: AES-XTS
Price: $14,000.00
* Target Technology

Xilinx

Intel (Altera)

Microsemi

Platinum - All FPGA Vendors [Add $2,000.00]

Lattice

* Implementation Language

VHDL

Verilog

Both VHDL and Verilog (option available for multi-project licenses only) [Add $2,000.00]
Please correct the following:

Description

XTS-AES Core - Encryption of Stored Data

This highly configurable implementation of the XTS-AES algorithm for storage encryption implements the full NIST SP800-38E specification used in IEEE standard 1619-2007. AES XTS is based on a pipelined implementation of AES to provide throughput to match multi-gigabit storage connection schemes such as USB 3.0 and SATA 3.0.

The AES-XTS core is based on our NIST validated AES-G3 implementation and is supplied as a complete package of VHDL or Verilog source code. The number of pipelined AES encryptors is configurable allowing a flexible tradeoff of area against performance.

AES XTS Core
Internal and External Data Path Width	128 bits
Cipher Modes	XTS, (if required ECB, CBC, CFB, OFB, CTR can be added)
Functions	Encrypt, Decrypt, Encrypt/Decrypt
Key Lengths	128, 256 bit AES Keys (256, 512 bit XTS-AES keys)
Keyschedule Calculation	Hardware keyschedule calculation.

Datasheets:

AES XTS Datasheet, Xilinx Edition



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