Description
Pipelined AES G3 Core for Video Encryption
This is a high performance pipelined implementation of AES optimized for encryption of uncompressed video on low cost FPGA families. This product delivers gigabit throughput with good area efficiency and is able to operate at high pixel clock frequency on lower cost FPGA devices. In video applications relatively long blocks of data will be encrypted between key changes, this assumption allows a more aggressive use of pipelining than in Algotronix AES cores optimized for networking. Encryption of compressed video requires less processing throughput than uncompressed video and is usually within the capabilities of the standard AES G3 core. The core is developed in accordance with Federal Information Processing Standards Publication (FIPS PUB 197) “Advanced Encryption Standard (AES)” and tested in accordance with the NIST document “The Advanced Encryption Standard Algorithm Validation Suite (AESAVS)”, November 15, 2002. The modes of operation are developed in accordance with the NIST document SP800-38A. This core is an extension of our NIST Validated (cert # 953) G3 AES core family and includes a license to the G3 product.
The G3 core is available as VHDL or Verilog source code.
Algotronix can also provide a design service to extend or tailor the core to meet the specific requirements of your application.
Datasheets and Applications Information:
Features
Low area, pipelined implementation of AES with moderate key latency suitable for video encryption/decryption.
Based on the NIST validated (Cert #953) AES-G3 implementation of the Advanced Encryption Standard
Supports 128, 192 and 256 bit keys
Targets all modern FPGA families from Xilinx, Altera, Lattice and Actel
High speed: can be clocked at pixel clock frequency even on low cost FPGA families
Supplied as easily customizable portable VHDL or Verilog to allow customers to conduct their own code review in high-security applications
Supplied with comprehensive test bench
