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AES Core G3

Our Price: (Members Only)

Product Code: AES-CORE-G3

Target Technology*:

Actel
Altera
Platinum - All FPGA Vendors [Add $2,000.00]
Xilinx

Description

The G3 AES core family is the third generation of Algotronix' AES technology. The G3 core is designed without compromise to be the most efficient and flexible implementation of AES available. A significant enhancement in the G3 product line is that the widths of internal and external data paths can be selected by the user using compilation parameters to allow an optimal tradeoff between area and performance. The G3 core thus supports a full range of AES implementations from ultra small cores targetting a CPLD to multi-gigabit parallelised cores running on advanced FPGAs. The G3 core also features an optimised implementation of the AES algorithm which allows it to process a block of data in fewer clock cycles than competitive products. G3 is supplied with a comprehensive testbench implementing the AESAVS test suite, the testbench can run qualification vectors from a NIST approved laboratory to provide an easy path the validation for user products using AES G3.

To request a no-cost evaluation of this product simply place the product in the shopping basket and enter the discount code EVAL on the checkout page.

Algotronix can also provide a design service to extend or tailor the core to meet the specific requirements of your application.

AES G3 Core
Internal Data Path Width	8, 16, 32, 64 or 128 bits
External Data Path Width	8, 16, 32, 64 or 128 bits (must be less than or equal to internal data path width)
Cipher Modes	ECB, CBC, CFB, OFB, CTR
Functions	Encrypt, Decrypt, Encrypt/Decrypt
Key Lengths	128, 192, 256 bits
Keyschedule Calculation	Hardware calculation or load keyschedule calculated in software. Extremely flexible implementation with many options.