This state of the art implementation of AES-GCM achieves 10Gbit/sec performance under worst case traffic conditions on Virtex 5 FPGAs. It implements AES-GCM as specified by the IEEE 802.1ae MACSEC standard.
Achieving 10Gbit/sec throughput on minimum sized packets with minimum inter-packet separation is a challenging task, particularly for an FPGA implementation where there are limitations on maximum clock frequency. The conventional approach to providing high performance on AES is to use a deep pipeline however this is ineffective on worst case traffic since minimum sized packets do not contain enough data to fill the pipeline. This core implements a pipelined and overlapped architecture with a number of proprietary implementation optimisations to deliver the required 10Gbit/sec performance even on worst case traffic. This core was developed to meet the requirements of a leading vendor of IP network test equipment and is currently in production.
This core is supplied as VHDL source code with a testbench which implements standard vectors from the GCM specification and a large test suite of vectors derived from a software implementation of AES-GCM.
