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AES Core GCM for 10Gbit/sec packet data
AES Core GCM for 10Gbit/sec packet data


 
Price: $16,000.00



Product Code: AES-GCM-10G


Target Technology*: 		Xilinx
Intel (Altera)
Microsemi
Platinum - All FPGA Vendors [Add $2,000.00]
Lattice

Implementation Language*: 		Both VHDL and Verilog (option available for multi-project licenses only) [Add $2,000.00]
Verilog
VHDL
Description Ordering Information
 

Advanced Encryption Standard Core GCM for IEEE 802.1 MACSEC at 10Gbit/sec

This state of the art implementation of AES-GCM achieves 10Gbit/sec performance under worst case traffic conditions on Virtex 5 FPGAs. It implements AES-GCM as specified by the IEEE 802.1ae MACSEC standard.

Achieving 10Gbit/sec throughput on minimum sized packets with minimum inter-packet separation is a challenging task, particularly for an FPGA implementation where there are limitations on maximum clock frequency. The conventional approach to providing high performance on AES is to use a deep pipeline however this is ineffective on worst case traffic since minimum sized packets do not contain enough data to fill the pipeline. This core implements a pipelined and overlapped architecture with a number of proprietary implementation optimisations to deliver the required 10Gbit/sec performance even on worst case traffic. This core was developed to meet the requirements of a leading vendor of IP network test equipment and is currently in production.

This core is supplied as VHDL source code with a testbench which implements standard vectors from the GCM specification and a large test suite of vectors derived from a software implementation of AES-GCM.

AES GCM 10GCore
Cipher Modes
AES-GCM as specified for 802.1ae MACSEC
Internal Data Path Width
128 bits with pipelining and overlapping
Functions
Encrypt, Decrypt, Encrypt/Decrypt
Key Lengths
128 or 256 bits
IV Length
96 bits
Datasheets:


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