Description
The AES-XTS core is based on our NIST validated AES-G3 implementation and is supplied as a complete package of VHDL or Verilog source code. The number of pipelined AES encryptors is configurable allowing a flexible tradeoff of area against performance.
AES XTS Core
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Internal and External Data Path Width
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128 bits
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Cipher Modes
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XTS, (if required ECB, CBC, CFB, OFB, CTR can be added)
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Functions
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Encrypt, Decrypt, Encrypt/Decrypt
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Key Lengths
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128, 256 bit AES Keys (256, 512 bit XTS-AES keys)
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Keyschedule Calculation
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Hardware keyschedule calculation.
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