AES GCM 10G Core - AES GCM Encryption IP Core for FPGAs, for IEEE 802.1 MACSEC at 10Gbit/sec

Description

Advanced Encryption Standard Core GCM for IEEE 802.1 MACSEC at 40Gbit/sec

This state of the art implementation of AES-GCM was originally designed to have sufficient performance to handle 40Gbit/sec Ethernet on Virtex 5 FPGAs. It will achieve significantly in excess of 40Gbit/sec on more modern devices. It implements AES-GCM as specified by the IEEE 802.1ae MACSEC standard.

Achieving 40Gbit/sec throughput on minimum sized packets with minimum inter-packet separation is a challenging task, particularly for an FPGA implementation where there are limitations on maximum clock frequency. The conventional approach to providing high performance on AES is to use a deep pipeline however this is ineffective on worst case traffic since minimum sized packets do not contain enough data to fill the pipeline. This core implements a pipelined and overlapped architecture with a number of proprietary implementation optimisations to deliver the required 40Gbit/sec performance even on worst case traffic.

This core is supplied as VHDL source code with a testbench which implements standard vectors from the GCM specification and a large test suite of vectors derived from a software implementation of AES-GCM.

AES GCM 40G
Cipher Modes	AES-GCM as specified for 802.1ae MACSEC
Internal Data Path Width	128 bits with pipelining and overlapping
Functions	Encrypt, Decrypt, Encrypt/Decrypt
Key Lengths	128 bits
IV Length	96 bits

Datasheets:

AES GCM 40G Datasheet, Xilinx Edition

AES-GCM IP Core for 40Gbit/sec packet data

AES-GCM IP Core for 40Gbit/sec packet data

Advanced Encryption Standard Core GCM for IEEE 802.1 MACSEC at 40Gbit/sec