Security IP Cores and Services

With around 100 design-ins across a range of target FPGA technologies Algotronix' Advanced Encryption Standard cores offer a well proven and competitively priced solution. Algotronix AES cores have been selected by many of the largest defense electronics companies and have been deployed by four NATO countries.

Our award winning DesignTag system allows labelling of the bitstream within an operating FPGA for intellectual property protection or version control purposes. DesignTag consists of a small, low power, IP core which is added to the design to be protected and DesignTag reader software and data logging hardware which senses the tag through the chip package and provides details of the protected product.

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IEEE 802.1ae MACSEC IP Core for 10 Gbit Ethernet AES Core XTS
The MACSEC core is a high performance pipelined implementation of IEEE standard 802.1ae. The core is built on
Algotronix' pipelined implementation of the AES-GCM encryption algorithm which itself builds on our G3 AES core.
AES XTS  Mode (XTS-AES)  IP Core for storage encryption implementing IEEE 1619-2007 and NIST Draft SP800-38E.