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Security IP Cores and Services

With more than 50 design-ins across a range of target FPGA technologies Algotronix' Advanced Encryption Standard cores offer a well proven and competitively priced solution. Algotronix AES cores have been selected by many of the largest defense electronics companies and have been deployed by four NATO countries.

Our award winning DesignTag system allows labelling of the bitstream within an operating FPGA for intellectual property protection or version control purposes. DesignTag consists of a small, low power, IP core which is added to the design to be protected and DesignTag reader software and data logging hardware which senses the tag through the chip package and provides details of the protected product.

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AES G3 Reference Design for Altera NIOS Processor AES Core G2

Our Price: (Members Only)

Our Price: (Members Only)
This reference design demonstrates how the AES-G3 core can be interfaced to an Altera NIOS II processor to accelerate AES encryption. G2 Advanced Encryption Standard (AES) Core with NIST validation certificate and 32 bit internal datapath width.