Advanced AES IP Cores
The Advanced Encryption Standard (AES), standardized by NIST in 2001 and approved by NSA for classified data, is at the heart of almost all modern data security protocols. With over 50 design-ins across a range of target FPGA technologies, Algotronix' Advanced Encryption Standard IP cores offer a well proven and competitively priced solution. Algotronix AES cores have been selected by many of the largest defense electronics companies and have been deployed by four NATO countries.
Algotronix supplies two families of AES cores. The low cost product range has a fixed 32 bit internal data path width and this advanced product range whith internal data path width parameterisable between 8, 16, 32, 64 or 128 bits. The advanced products also offer extra flexibility in key calculation and in some cases parallelisation. This allows the advanced products to efficiently address a much wider spectrum of application requirements than the low cost products. The advanced products are likely to have superior area and power consumption for low performance applications and a much higher maximum throughput.
The G3 AES core which is at the heart of the advanced product range supports all the standard AES modes: ECB, CBC, OFB, CFB1, CFB8, CFB128 and CTR as well as 128, 192 or 256 bit key length and key-schedule generation in hardware or software.
The AES-GCM Core implements the Galois Counter Mode of operation of the AES algorithm. GCM has been widely adopted because it provides authentication and confidentiality in addition to the encryption function. The Algotronix AES-GCM core provides a solution for medium to high speed systems.
Very high speed systems of 10Gbit/sec and above use the “10G” version of the GCM core. The AES-GCM 10G is the only core guaranteed to meet data transfers of 10Gbit/sec in an FPGA. It is an expanded and optimized variant of AES-GCM. The core delivers 10Gbit/sec worst-case performance on the GCM processing required for IEEE 802.1 MACSEC even on a stream of minimum size packets with a key change on each packet.
The AES-CCM Core implements the Counter with CBC MAC Mode of operation of the AES algorithm. Like GCM, CCM provides authentication and confidentiality in addition to the encryption function and is widely used in wireless networking applications.
The AES-Keywrap core implements a NIST approved mechanism for 'wrapping' cryptographic keys and other critical security parameters in order to transfer them over an insecure communications medium. Safely introducing key material into the encryption system is a requirement in many applications and AES Keywrap is particularly area efficient because it can make use of the same AES encryptor used to encrypt data traffic.
The encryption cores are supplied as a complete package of VHDL or Verilog source code. The IP cores can be targeted at FPGAs from Xilinx, Altera and Actel as well as ASIC or even CPLD implementations. Source code reduces the cost and complexity of a security audit. It allows customers to confirm that no virus or Trojan code is incorporated and that it cannot be forced into unauthorised states or operations. This can significantly reduce the cost and time to conduct a security audit. Demonstration designs are available which show the cores working on low cost vendor evaluation boards.
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